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the information in this document is subject to change without notice. before using this document, please confirm that this is the latest version. not all devices/types available in every country. please check with local nec representative for availability and additional information. ? 2001 mos integrated circuit pd23c256112a nand interface 256m-bit mask-programmable rom data sheet document no. m15902ej2v0ds00 (2nd edition) date published september 2002 ns cp (k) printed in japan the mark shows major revised points . description the pd23c256112a is a 256 mbit nand interface programmable mask read-only memory that operates with a single power supply. the memory organization consists of (512 + 16 (redundancy)) bytes x 32 pages x 2,048 blocks. the pd23c256112a is a serial type mask rom in which addresses and commands are input and data output serially via the i/o pins. the pd23c256112a is packed in 48-pin plastic tsop(i). features ? word organization (33,554,432 + 1,048,576 note ) words by 8 bits ? page size (512 + 16 note ) by 8 bits ? block size (16,384 + 512 note ) by 8 bits note underlined parts are redundancy. caution redundancy is not programmable parts and is fixed to all ffh. ? operation mode read mode (1), read mode (2), read mode (3), reset, status read, id read ? operating supply voltage : v cc = 3.3 0.3 v ? access time memory cell array to starting address : 7 s (max.) read cycle time : 50 ns (min.) /re access time : 35 ns (max.) ? operating supply current during read : 30 ma (max.) (50 ns cycle operation) during standby (cmos) : 100 a (max.) ordering information part number package pd23c256112agy- xxx-mjh 48-pin plastic tsop(i) (12x18) (normal bent) pd23c256112agy- xxx-mkh 48-pin plastic tsop(i) (12x18) (reverse bent) (xxx : rom c ode suffix no.)
data sheet m15902ej2v0ds 2 pd23c256112 a pin configurations /xxx indicates active low si gnal. 48-pin plastic tsop(i) (12x18) (normal bent) [ pd23c256112agy-xxx-mjh ] marking side nc nc nc ic ic gnd r, /b /re /ce nc nc v cc v ss nc nc cle ale /we ic ic ic nc nc nc nc nc nc nc i/o7 i/o6 i/o5 i/o4 nc nc nc v cc v ss nc nc nc i/o3 i/o2 i/o1 i/o0 nc nc nc nc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 i/o0 to i/o7 : address inputs / command inputs / data outputs cle : command latch enable input ale : address latch enable input /we : write enable input /re : read enable input /ce : chip enable input r, /b note1 : ready, /busy output v cc : supply voltage vss : ground nc note2 : no connection ic note3 : internal connection gnd : gnd notes 1. this pin is an open-drain output pin. therefore, a pull-up resistor is required when using this pin. 2. some signals can be applied because this pin is not connected to the inside of the chip. 3. leave this pin unconnected or connected to v ss . remark refer to package drawings for the 1-pin index mark.
data sheet m15902ej2v0ds 3 pd23c256112 a 48-pin plastic tsop(i) (12x18) (reverse bent) [ pd23c256112agy-xxx-mkh ] marking side nc nc nc ic ic gnd r, /b /re /ce nc nc v cc v ss nc nc cle ale /we ic ic ic nc nc nc nc nc nc nc i/o7 i/o6 i/o5 i/o4 nc nc nc v cc v ss nc nc nc i/o3 i/o2 i/o1 i/o0 nc nc nc nc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 i/o0 to i/o7 : address inputs / command inputs / data outputs cle : command latch enable input ale : address latch enable input /we : write enable input /re : read enable input /ce : chip enable input r, /b note1 : ready, /busy output v cc : supply voltage vss : ground nc note2 : no connection ic note3 : internal connection gnd : gnd notes 1. this pin is an open-drain output pin. therefore, a pull-up resistor is required when using this pin. 2. some signals can be applied because this pin is not connected to the inside of the chip. 3. leave this pin unconnected or connected to v ss . remark refer to package drawings for the 1-pin index mark.
data sheet m15902ej2v0ds 4 pd23c256112 a input / output pin functions pin name input / output function i/o0 to i/o7 (address inputs / command inputs / data outputs) input, output i/o port for address input, command input, and data output. i/o pins. cle (command latch enable input) input input pin for signal for controlling loading of commands to command register in device. by making this signal high level at the rising edge or falling edge of the /we signal, the data of the i/o0 to i/o7 pins is loaded to the command register as commands. ale (address latch enable input) input input pin for signal for controlling loading of address data to the address register in the device. by making this signal high level at the rising edge or falling edge of the /we signal, the data of the i/o0 to i/o7 pins is loaded as address. /we (write enable input) input input pin for signal for loading the data from the i/o0 to i/o7 pins inside the device. /re (read enable input) input input pin for signal for serially outputting data. the output data of i/o0 to i/o7 is determined after t rea from the falling edge of the /re signal, and the internal address counter is incremented by +1 at the rising edge of the /re signal. /ce (chip enable input) input input pin for device selection signal. during read, the standby mode is entered by making this signal high level. r, /b (ready, /busy output) output output pin for signal that notifies the internal operating status of the device to external. this is an open-drain output signal. during read, busy is output during operation (r, /b = low level), and upon completion, ready (r, /b = high level) is automatically output.
data sheet m15902ej2v0ds 5 pd23c256112 a block diagram i/o0 i/o1 i/o2 i/o3 i/o4 i/o5 i/o6 i/o7 /ce cle ale /we /re input / output buffer x-decoder control logic read contorol circuit ready/busy control circuit command register address register id register status register dara register circuit r, /b (open-drain) sense amplifier y-selector memory cell matrix vcc vss
data sheet m15902ej2v0ds 6 pd23c256112 a memory area 0 ? 255 256 511 527 (a) (b) (c) 2,048 blocks = 65,536 pages 512 bytes (main memory) 16 bytes (redundancy) 0 1 2 30 31 65,533 65,534 65,535 1 page = 528 bytes 1 block = 32 pages ? the start address (sa) during read operation is specified divided into three areas using three types of read commands. in read mode (1), start address (sa) is set in area (a). in read mode (2), start address (sa) is set in area (b). in read mode (3), start address (sa) is set in area (c). one page consists of a total of 528 bytes broken down into 512 bytes (main memory) and 16 bytes (redundancy). one block consists of 32 pages. caution the data of area (c) is redundancy. redundancy is not programmable parts and is fixed to all ffh.
data sheet m15902ej2v0ds 7 pd23c256112 a operation modes command input, address input, and serial read are all performed from i/o pins, and the respective statuses are controlled by the cle, ale, /we, /re, and /ce signals. cle ale i/o0 to i/o7 command input cycle address input cycle serial read cycle busy /ce /we /re r, /b high-z high-z high-z operation mode mode cle ale /ce /we /re command input cycle h l l h address input cycle l h l h serial read cycle l l l h operation mode during serial read mode cle ale /ce /we /re i/o0 to i/o7 data output l l l h l data output output high-z l l l h h high-z standby l l h h high-z remark : v ih or v il
data sheet m15902ej2v0ds 8 pd23c256112 a operation commands the following six operation settings are possible by inputting commands from i/o pins. command hex i/o7 i/o6 i/o5 i/o4 i/o3 i/o2 i/o1 i/o0 command receivable during busy read mode(1) 00h l l l l l l l l read mode(2) 01h l l l l l l l h read mode(3) note1 50hlhlhllll reset note2 ffhhhhhhhhh status read 70h l h h h l l l l id read note3 90hhllhllll notes 1. the data output in read mode (3) is all ffh. 2. the only command that can be executed when the device is busy is the reset command. do not set any of the other commands while the device is busy. 3. for id read, input ?00h? during the first address cycle after setting a command. i/o pin correspondence table during address input cycle (address setting) (1) when 00h or 01h command is set [read mode (1), read mode (2)] command i/o7 i/o6 i/o5 i/o4 i/o3 i/o2 i/o1 i/o0 1st address cycle a7 a6 a5 a4 a3 a2 a1 a0 2nd address cycle a16 a15 a14 a13 a12 a11 a10 a9 3rd address cycle a24 a23 a22 a21 a20 a19 a18 a17 (2) when 50h command is set [read mode (3)] command i/o7 i/o6 i/o5 i/o4 i/o3 i/o2 i/o1 i/o0 1st address cycle a3 a2 a1 a0 2nd address cycle a16 a15 a14 a13 a12 a11 a10 a9 3rd address cycle a24 a23 a22 a21 a20 a19 a18 a17 remarks 1. a0 to a24 are internal addresses. 2. internal address a8 is set internally with command 00h or 01h. 3. when 50h command is set [read mode (3)], the i/o4, i/o5, i/o6, and i/o7 inputs of the 1st address cycle are v ih or v il .
data sheet m15902ej2v0ds 9 pd23c256112 a (1) rated operation operation using timing other than shown in the timing charts is not guaranteed. (2) commands that can be input the only commands that can be input are 00h, 01h, 50h, 70h, 90h, and ffh. do not input any other commands. if other commands are input, the subsequent operation is not guaranteed. (3) command limitations during busy period do not input commands other than the reset command (ffh) during the busy period. if a command is input during the busy period, the subsequent operation is not guaranteed. (4) cautions regarding /re clock ? following the last /re clock, do not input the /re clock until the r, /b pin changes from busy to ready. ? do not input the /re clock other than during data output. (5) cautions upon power application since the state of the device is undetermined upon power on, input high level to the /ce pin and execute the reset command following power on. (6) cautions during read mode ? perform address input immediately following command input. if address input is done without performing command input first, the correct data cannot be output because the operation mode is undetermined. ? to execute the read mode after the read mode has been stopped with the reset command (ffh) and /ce, input again a command and address. (7) busy output following access of last address in page in read mode after the access to the last address in a page, if the delay (t rhch ) from /re to /ce is 30 ns or less, the ready status is maintained and busy is not output by keeping /ce high level for a set period (t ceh ). t ceh t rhch /ce /re r, /b 527 526 usa g e cautions
data sheet m15902ej2v0ds 10 pd23c256112 a electrical specifications absolute maximum ratings parameter symbol condition rating unit supply voltage v cc ?0.5 to +4.6 v input voltage v i ?0.3 to v cc +0.3 v input / output voltage v i/o ?0.3 to v cc +0.3 ( 4.6) v operating ambient temperature t a 0 to 70 c storage temperature t stg ?65 to +150 c caution exposing the device to stress above those listed in absolute maximum ratings could cause permanent damage. the device is not meant to be operated under conditions outside the limits described in the operational section of this specification. exposure to absolute maximum rating conditions for extended periods may affect device reliability. capacitance (t a = 25c) parameter symbol test condition min. typ. max. unit input capacitance c i 10 pf output capacitance c o f = 1 mhz 10 pf dc characteristics (t a = 0 to 70c, v cc = 3.3 0.3 v) parameter symbol test conditions min. typ. max. unit high level input voltage v ih 2.0 v cc + 0.3 v low level input voltage v il ?0.3 +0.8 v high level output voltage v oh i oh = ?400 a2.4 v low level output voltage v ol i ol = 2.1 ma 0.4 v input leakage current i li v i = 0 v to v cc 10 a output leakage current i lo v o = 0 v to v cc 10 a power supply current in read i cco1 /ce = v il , i out = 0 ma, t cycle = 50 ns 30 ma power supply current in command input i cco3 t cycle = 50 ns 30 ma power supply current in address input i cco5 t cycle = 50 ns 30 ma standby current (ttl) i ccs1 /ce = v ih 1ma standby current (cmos) i ccs2 /ce = v cc ? 0.2 v 100 a (r, /b) pin output current i ol(r, /b) v ol = 0.4 v 8 ma
data sheet m15902ej2v0ds 11 pd23c256112 a ac characteristics (t a = 0 to 70c, v cc = 3.3 0.3 v) parameter symbol min typ. max. unit cle setup time t cls 0ns cle hold time t clh 10 ns /ce setup time t cs 0ns /ce hold time t ch 10 ns write pulse width t wp 25 ns ale setup time t als 0ns ale hold time t alh 10 ns data setup time t ds 20 ns data hold time t dh 10 ns write cycle time t wc 50 ns /we high hold time t wh 15 ns ready to /re falling edge t rr 20 ns read pulse width t rp 35 ns read cycle time t rc 50 ns /re access time (serial data access) t rea 35 ns /ce high hold time for last address in serial read cycle t ceh 100 ns /re access time (id read ) t reaid 35 ns /re high to output high-z t rhz 10 30 ns /ce high to output high-z t chz 20 ns /re high hold time t reh 15 ns output high-z to /re falling edge t ir 0ns /re access time (status read) t rsto 35 ns /ce access time (status read) t csto 45 ns /we high to /ce low t whc 30 ns /we high to /re low t whr 30 ns ale low to /re low (id read) t ar1 100 ns /ce low to /re low (id read) t cr 100 ns memory cell array to starting address t r 7 s /we high to busy t wb 200 ns ale low to /re low (read cycle) t ar2 50 ns /re last clock rising edge to busy (in sequential read) t rb 200 ns /ce high to ready (when interrupted by /ce in read mode) t cry note 1 s device reset time t rst 6 s note t cry (time from /ce high to ready) depends on the pull-up resister of the r, /b output pin.
data sheet m15902ej2v0ds 12 pd23c256112 a ac test conditions input waveform (rise / fall time 5 ns) 1.5 v 1.5 v test points output waveform 1.5 v 1.5 v test points output load 1 ttl + 100 pf
data sheet m15902ej2v0ds 13 pd23c256112 a 00h d out d out a17 to a24 a9 to a16 d out a0 to a7 t cls t cs t clh t ch t cs t ceh t wc t r t alh t als t wp t wh t alh t ar2 t cry t chz t rr t rc t rc t rp t reh t rhz t rhz t rb t rea t dh t dh t dh t ds t dh t ds t ds t ds t wb access page m output page m data n n+1 527 cle ale i/o0 to i/o7 /ce /we /re r, /b read cycle timing chart (1) (in case of read mode (1)) remarks 1. start address (sa) specification when read is performed with command 00h. n: 0 to 255 2. then time (t cry ) from /ce high to ready is cancelled depends on the pull-up register of the r,/b output pin. high-z high-z
data sheet m15902ej2v0ds 14 pd23c256112 a 01h d out d out a17 to a24 a9 to a16 d out a0 to a7 t cls t cs t clh t ch t cs t ceh t wc t r t alh t als t wp t wh t alh t ar2 t cry t chz t rr t rc t rc t rp t reh t rhz t rhz t rb t rea t dh t dh t dh t ds t dh t ds t ds t ds t wb 256 + n 256 + n + 1 527 cle ale i/o0 to i/o7 /ce /we /re r, /b access page m output page m data read cycle timing chart (2) (in case of read mode (2)) remarks 1. start address (sa) specification when read is performed with command 01h. n: 0 to 255 2. then time (t cry ) from /ce high to ready is cancelled depends on the pull-up register of the r,/b output pin. high-z high-z
data sheet m15902ej2v0ds 15 pd23c256112 a 50h d out d out a17 to a24 a9 to a16 d out a0 to a3 t cls t cs t clh t ch t cs t ceh t wc t r t alh t als t wp t wh t alh t ar2 t cry t chz t rr t rc t rc t rp t reh t rhz t rhz t rb t rea t dh t dh t dh t ds t dh t ds t ds t ds t wb 512 + n 512 + n + 1 527 cle ale i/o0 to i/o7 /ce /we /re r, /b access page m output page m data read cycle timing chart (3) (in case of read mode (3)) remarks 1. start address (sa) specification when read is performed with command 50h. n: 0 to 15 2. the start address of area c (redundancy data) is specified with a0 to a3 during the 1st address cycle. at this time, a4 to a 7 are don't care. 3. the time (t cry ) from /ce high to ready is cancelled depends on the pull-up register of the r, /b output pin. 4. the data that is output is ffh. high-z high-z
data sheet m15902ej2v0ds 16 pd23c256112 a d out d out d out t cls t cs t clh t ch t cs t wc t r t alh t als t wp t wh t alh t ar2 t chz t rr t rc t rc t rp t reh t rhz t rhz t rea t dh t dh t dh t ds t dh t ds t ds t ds t wb n n + 1 n + 2 cle ale i/o0 to i/o7 /ce /we /re r, /b access page m command input read cycle timing chart (4) (when /ce is made high level in the read mode) remark if /ce is made high level during the read cycle, the read operation until that time is cancelled. therefore, to perform read again, execute a new command and new address input. address input address input address input high-z high-z
data sheet m15902ej2v0ds 17 pd23c256112 a sequential read in read modes (1), (2), and (3), when a command (00h, 01h, 50h) is input and an address specified, if it is in the block that includes the address that was specified first, the address is automatically incremented and the read operation is continuously performed until the last address in the same block, by inputting the /re clock. at this time, a busy period (t r ) occurs after the last address is accessed in a page. busy busy busy busy busy busy in same block (maximum of 32 pages) 00h 01h 50h 00h 01h 50h t r t r t r t r t r t cry command input address input page m data output page m+1 data output output of in last page in block address input data output command input note note r, /b note to perform read again after reading the 527th byte of data of the last page of block, stop the read operation once, and then restart the read operation by inputting again the read command and an address. relationship between command and start address (sa) during sequential read 0 256 512 527 (a) (b) (c) 1 block = 32 pages sa 0 256 512 527 (a) (b) (c) sa 0 256 512 527 (a) (b) (c) sa sequential read mode (1) (when "00h" command is input) sequential read mode (2) (when "01h" command is input) sequential read mode (3) (when "50h" command is input) note note when the "50h" command is set, only the (c) area (redundancy data part) is continuously read. ? when the ?00h? command is set, the start address (sa) is set to area (a). ? when the ?01h? command is set, the start address (sa) is set to area (b). ? when the ?50h? command is set, the start address (sa) is set to area (c).
data sheet m15902ej2v0ds 18 pd23c256112 a 00h d out d out a17 to a24 a9 to a16 d out a0 to a7 t cls t cs t clh t ch t cs t wc t r t alh t als t wp t wh t alh t ar2 t rr t rc t rc t rp t reh t rhz t rb t rea t dh t dh t dh t ds t dh t ds t ds t ds t wb n n + 1 527 d out t rr d out 1 0 t r cle ale i/o0 to i/o7 /ce /we /re r, /b access page m output page m data sequential read cycle timing chart (1) (in case of read mode (1)) remark start address (sa) specification when read is performed with command 00h. n: 0 to 255 access page m+1 output page m+1 data high-z high-z high-z
data sheet m15902ej2v0ds 19 pd23c256112 a 01h d out d out a17 to a24 a9 to a16 d out a0 to a7 t cls t cs t clh t ch t cs t wc t r t alh t als t wp t wh t alh t ar2 t rr t rc t rc t rp t reh t rhz t rb t rea t dh t dh t dh t ds t dh t ds t ds t ds t wb 256 + n 256 + n + 1 527 d out t rr d out 1 0 t r cle ale i/o0 to i/o7 /ce /we /re r, /b access page m output page m data sequential read cycle timing chart (2) (in case of read mode (2)) remark start address (sa) specification when read is performed with command 01h. n: 0 to 255 access page m+1 output page m+1 data high-z high-z high-z
data sheet m15902ej2v0ds 20 pd23c256112 a 50h d out d out a17 to a24 a9 to a16 d out a0 to a3 t cls t cs t clh t ch t cs t wc t r t alh t als t wp t wh t alh t ar2 t rr t rc t rc t rp t reh t rhz t rb t rea t dh t dh t dh t ds t dh t ds t ds t ds t wb 512 + n 512 + n + 1 527 d out t rr d out 513 512 t r cle ale i/o0 to i/o7 /ce /we /re r, /b access page m output page m data sequential read cycle timing chart (3) (in case of read mode (3)) remark start address (sa) specification when read is performed with command 50h. n: 0 to 15 access page m+1 output page m+1 data high-z high-z high-z
data sheet m15902ej2v0ds 21 pd23c256112 a status read status information can be output from the i/o pins with the /re clock following input of the 70h command. status read is a function to recognize the status of the device from external. cle i/o0 to i/o7 t cls ready 70h status t clh t cs t ch t csto t whc t chz t rhz t whr t ds t dh t ir t rsto t cls /ce /we /re r, /b t wp high-z high-z status status output data note i/o0 ready / busy 0 / 1 i/o1 not used 0 i/o2 not used 0 i/o3 not used 0 i/o4 not used 0 i/o5 not used 0 i/o6 ready / busy 1 / 0 i/o7 write protect 0 note use the status read command only during ready.
data sheet m15902ej2v0ds 22 pd23c256112 a id read to recognize the id code (maker code / device code) of this device in a system, execute the id read command. the id code can be read with the following timing. cle t cls 90h 10h t clh t cs t ch t ds t dh t reaid t cls 58h 00h ale t reaid t rp t reh t ds t dh t cs t ch t cr t als t alh t wp t alh t ar1 t rc /ce /we /re maker code device code i/o0 to i/o7 high-z i/o7 i/o6 i/o5 i/o4 i/o3 i/o2 i/o1 i/o0 hex maker code l l l h l l l l 10h device code l h l h h l l l 58h cautions 1. if the /re clock is input after the maker code and device code are output, the output data is not guaranteed. therefore, do not input the /re clock following device code output. 2. do not input an address other than 00h after setting the id read command (90h). if an address other than 00h is input, the data following /re clock input is not guaranteed.
data sheet m15902ej2v0ds 23 pd23c256112 a reset cycle timing chart cle i/o0 to i/o7 t cls t clh t ds t dh ale t als t alh t cs t ch t wb ffh t rst /ce /we r, /b t wp
data sheet m15902ej2v0ds 24 pd23c256112 a package drawings notes 48-pin plastic tsop( i ) (12x18) item millimeters a b c e i 12.0 0.1 0.5 (t.p.) 0.1 0.05 0.45 max. k 1.2 max. 16.4 0.1 0.145 0.05 f 0.10 m d 0.22 0.05 1. each lead centerline is located within 0.10 mm of its true position (t.p.) at maximum material condition. 2. "a" excludes mold flash. (includes mold flash : 12.4 mm max.) r k l 1.0 0.05 g l 0.5 0.10 n p 18.0 0.2 q3 + 5 ? 3 0.25 r s48gy-50-mjh1-1 s 0.60 0.15 j 0.8 0.2 s q s n e g f j detail of lead end c d m m b a i p 1 24 48 25 s
data sheet m15902ej2v0ds 25 pd23c256112 a 0.145 0.05 notes 48-pin plastic tsop( i ) (12x18) item millimeters a b c e i 12.0 0.1 0.5 (t.p.) 0.1 0.05 0.45 max. k 1.2 max. 16.4 0.1 f 0.10 m d 0.22 0.05 1. each lead centerline is located within 0.10 mm of its true position (t.p.) at maximum material condition. 2. "a" excludes mold flash. (includes mold flash : 12.4 mm max.) c b r k d m m 1.0 0.05 g l 0.5 0.10 n p 18.0 0.2 q3 + 5 ? 3 0.25 r s48gy-50-mkh1-1 s 0.60 0.15 j 0.8 0.2 s n j g f l s q e detail of lead end 1 24 48 25 s a i p
data sheet m15902ej2v0ds 26 pd23c256112 a recommended soldering conditions please consult with our sales offices for soldering conditions of the pd23c256112a. types of surface mount device pd23c256112agy-mjh : 48-pin plastic tsop(i) (12x18) (normal bent) pd23c256112agy-mkh : 48-pin plastic tsop(i) (12x18) (reverse bent)
data sheet m15902ej2v0ds 27 pd23c256112 a revision history edition/ page type of location description date this previous revision (previous edition this edition) edition edition 2nd edition/ p.1 p.1 modification features read cycle time: sep. 2002 50ns(max.) 50ns(min.) p.4 p.4 modification input/output pin functions signal descriptions input/output pin functions p.9 p.23 modification usage cautions moved in front of electrical specifications page
data sheet m15902ej2v0ds 28 pd23c256112 a [ memo ]
data sheet m15902ej2v0ds 29 pd23c256112 a [ memo ]
data sheet m15902ej2v0ds 30 pd23c256112 a [ memo ]
data sheet m15902ej2v0ds 31 pd23c256112 a notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed immediately after power-on for devices having reset function.
pd23c256112 a m8e 00. 4 the information in this document is current as of september, 2002. the information is subject to change without notice. for actual design-in, refer to the latest publications of nec's data sheets or data books, etc., for the most up-to-date specifications of nec semiconductor products. not all products and/or types are available in every country. please check with an nec sales representative for availability and additional information. no part of this document may be copied or reproduced in any form or by any means without prior written consent of nec. nec assumes no responsibility for any errors that may appear in this document. nec does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of nec semiconductor products listed in this document or any other liability arising from the use of such products. no license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec or others. descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software and information in the design of customer's equipment shall be done under the full responsibility of customer. nec assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. while nec endeavours to enhance the quality, reliability and safety of nec semiconductor products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. to minimize risks of damage to property or injury (including death) to persons arising from defects in nec semiconductor products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment, and anti-failure features. nec semiconductor products are classified into the following three quality grades: "standard", "special" and "specific". the "specific" quality grade applies only to semiconductor products developed based on a customer-designated "quality assurance program" for a specific application. the recommended applications of a semiconductor product depend on its quality grade, as indicated below. customers must check the quality grade of each semiconductor product before using it in a particular application. "standard": computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots "special": transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) "specific": aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. the quality grade of nec semiconductor products is "standard" unless otherwise expressly specified in nec's data sheets or data books, etc. if customers wish to use nec semiconductor products in applications not intended by nec, they must contact an nec sales representative in advance to determine nec's willingness to support a given application. (note) (1) "nec" as used in this statement means nec corporation and also includes its majority-owned subsidiaries. (2) "nec semiconductor products" means any semiconductor product developed or manufactured by or for nec (as defined above). ? ? ? ? ? ? the export of this product from japan is regulated by the japanese government. to export this product may be prohibited without governmental license, the need for which must be judged by the customer. the export or re-export of this product from a country other than japan may also be prohibited without a license from that country. please call an nec sales representative.

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